This invention relates to an input bias current reduction circuit for multiple input stages having a common input.
Many circuits exhibit an undesirable nonzero input bias current which causes an offset voltage from the source voltage as it flows through the source impedance. A fixed offset voltage can often be compensated, but one that varies (e.g. with temperature or system configuration) is more troublesome. In a video system, the source impedance is typically 75xcexa9 or 37.5xcexa9 and offsets are perceived as variations in the video black level. It is desirable to reduce the input bias current, and the variation thereof, of a circuit having an input lead that is shared by a number (N) of input stages. Such a configuration can be found at each input of an (M input by N output) analog video cross point switch implemented using bipolar transistors. Each input stage on a given input line corresponds to an output to which that input signal may be routed; an input may be connected to anywhere from zero to N outputs via these input stages. In this case, the bias current of an input stage corresponds to the base current of a bipolar transistor, which is strongly dependent upon temperature and process variations. If the N input stages of the crosspoint are nominally identical, then the input bias current seen at the input lead can vary from nearly zero (in the case where that input is not routed to any of the outputs) to N times greater than that of any input stages (in the broadcast mode where that input is routed to all of the outputs).
A video crosspoint switch typically has a plurality of input stages arranged in rows and columns. All of the input stages in a column are connected to a common input and any one or more of them may be receiving an input at any time. Each input stage includes an input transistor whose base to emitter leakage current loads the common input and causes variations in the input current which fluctuates with the number of input stages in that column that are on. The base to emitter leakage current introduces errors in the response of the input stage; and the fluctuation of the error with the number of input stages that are on compounds the problem. One solution has been to add a buffer stage in each common input to each column so that no matter what the total current leakage or how it varies the voltage of the input signal will remain constant. However, the provision of this buffer adds area, transistors, power, noise and distortion. In another approach each stage has added to it a replication circuit which senses the leakage current in that stage and adds that current back to offset the error in that stage. This approach adds significant area to each stage and is multiplied by the number of stages.
It is therefore an object of this invention to provide an improved input bias current reduction circuit for multiple input stages having a common input.
It is a further object of this invention to provide such an improved input bias current reduction circuit which is simple, small, and easy to implement.
It is a further object of this invention to provide an improved input bias current reduction circuit which does not significantly add to the area, power or transistors required or to noise and distortion.
It is a further object of this invention to provide an improved input biased current reduction circuit which can also serve to provide a conventional voltage bias to each input stage.
The invention results from the realization that a more precise compensation for input bias leakage current in multiple input stages with a common input can be achieved by measuring the leakage current in each input stage connected to the common input and then replicating the current for all the input stages connected to the same common input and subtracting that current from the input.
This invention features an input bias current reduction circuit for multiple input stages having a common input. There are a plurality of input stages each including a first input transistor with its base connected to the common input and the first current sensing transistor with its collected-emitter in series with the collector-emitter of the first input transistor and its base current replicating that of the first transistor. A current compensation circuit senses the base current of the first current sensing transistor in each input stage and subtracts that from the base current of the first input transistor in each input stage for maintaining constant reduced current loading of the input.
In a preferred embodiment each input stage may include a second input transistor. The first current sensing transistor may be cascode connected to the first input transistor. The first current sensing transistor may be cascode connected to the first input transistor and there may be a second current sensing transistor cascode connected to the second input transistor. The first and the second input transistors may be emitter coupled and they may form a differential amplifier. The bases of the first and second current sensing transistors may be connected together. The transistors may be bipolar. The current compensation circuit may include a current mirror and it may include an idle current source. The current compensation circuit may be connected to a voltage source and may provide a bias voltage to the current sensing transistors. The first input transistor may be common emitter connected.